Method for sorting integrated circuit devices

ABSTRACT

A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/248,700, filed Oct. 9, 2008, pending, which is a continuation ofapplication Ser. No. 10/092,185, filed Mar. 6, 2002, now U.S. Pat. No.7,446,277, scheduled to issue Nov. 4, 2008, which is a continuation ofapplication Ser. No. 09/941,092, filed Aug. 28, 2001, now U.S. Pat. No.6,373,011, issued Apr. 16, 2002, which is a continuation of applicationSer. No. 09/713,912, filed Nov. 15, 2000, now U.S. Pat. No. 6,365,861,issued Apr. 2, 2002, which is a division of application Ser. No.09/520,067, filed Mar. 7, 2000, now U.S. Pat. No. 6,350,959, issued Feb.26, 2002, which is a continuation of application Ser. No. 09/133,338,filed Aug. 13, 1998, now U.S. Pat. No. 6,100,486, issued Aug. 8, 2000,which is a division of application Ser. No. 08/785,353, filed Jan. 17,1997, now U.S. Pat. No. 5,927,512, issued Jul. 27, 1999. The disclosureof the previously referenced patent applications and patents are beingincorporated by reference in their entirety.

The present application is also related to: application Ser. No.08/591,238, filed Jan. 17, 1996, now abandoned; application Ser. No.08/664,109, filed Jun. 13, 1996, now U.S. Pat. No. 5,895,962, issuedApr. 20, 1999; a divisional application having Ser. No. 09/133,336,filed Aug. 13, 1998, now U.S. Pat. No. 6,147,316, issued Nov. 14, 2000;a application having Ser. No. 08/822,731, filed Mar. 24, 1997, now U.S.Pat. No. 5,856,923, issued Jan. 5, 1999; a application having Ser. No.08/806,442, filed Feb. 26, 1997, now U.S. Pat. No. 5,915,231, issuedJun. 22, 1999; a application having Ser. No. 08/871,015, filed Jun. 6,1997, now U.S. Pat. No. 5,907,492, issued May 25, 1999; and aapplication having Ser. No. 08/801,565 filed Feb. 17, 1997, now U.S.Pat. No. 5,844,803, issued Dec. 1, 1998.

STATE OF THE ART

Integrated circuits (ICs) are small electronic circuits formed on thesurface of a wafer of semiconductor material, such as silicon, in an ICmanufacturing process referred to as “fabrication.” Once fabricated, ICsare electronically probed to evaluate a variety of their electroniccharacteristics, cut from the wafer on which they were formed intodiscrete IC dice or “chips,” and then assembled for customer use usingvarious well-known IC packaging techniques, including lead framepackaging, Chip-On-Board (COB) packaging, and flip-chip packaging.

Before being shipped to customers, packaged ICs are generally tested toensure they will function properly once shipped. Testing typicallyinvolves a variety of known test steps, such as pre-grade, burn-in, andfinal, which test ICs for defects and functionality and grade ICs forspeed. As shown in FIG. 1, ICs that pass the described testing aregenerally shipped to customers, while ICs that fail the testing aretypically rejected.

The testing standards for a particular IC product are sometimes relaxedas the product “matures,” such that ICs previously rejected under stricttesting standards may pass the relaxed testing standards. Consequently,reject bins containing previously rejected ICs are sometimes “culled”for ICs that are shippable under relaxed testing standards by testingthe rejected ICs again using the relaxed testing standards.Unfortunately, while this culling process does retrieve shippable ICsfrom reject bins, it makes inefficient use of expensive and oftenlimited testing resources by diverting those resources away from testinguntested ICs in order to retest previously rejected ICs. Therefore,there is a need in the art for an improved method of culling or sortingsuch reject bins for shippable ICs.

Similarly, as shown in FIG. 2, all the ICs from the wafers in a waferlot typically undergo enhanced reliability testing that is moreextensive and strict than normal testing when any of the wafers in thelot are deemed to be unreliable because of fabrication or other processerrors. Since a wafer lot typically consists of 50 or more wafers, manyof the ICs that undergo the enhanced reliability testing do not requireit because they come from wafers that are not deemed unreliable.Performing enhanced reliability testing on ICs that do not need it isinefficient because such testing is typically more time-consuming anduses more resources than normal testing. Therefore, there is a need inthe art for a method of sorting ICs from a wafer lot into those ICs thatrequire enhanced reliability testing and those that do not.

Likewise, as shown in FIG. 3, a new or special “recipe” for fabricatingICs on wafers is sometimes tested by fabricating some wafers from awafer lot using the special recipe and other wafers from the wafer lotusing a control recipe. ICs from the wafers then typically undergoseparate assembly and test procedures so that the test results of ICsfabricated using the special recipe are not mixed with the test resultsof ICs fabricated using the control recipe, and vice versa. Test reportsfrom the separate test procedures are then used to evaluate the specialrecipe and to determine whether the ICs are to be shipped to customers,reworked, repaired, retested, or rejected. Unfortunately, because theICs undergo separate test and assembly procedures, undesirablevariables, such as differences in assembly and test equipment, areintroduced into the testing of the special recipe. It would bedesirable, instead, to be able to assemble and test the ICs using thesame assembly and test procedures, and to then sort the ICs and theirtest results into those ICs fabricated using the special recipe andthose ICs fabricated using the control recipe. Therefore, there is aneed in the art for a method of identifying individual ICs fabricatedusing a special or control recipe and sorting the ICs based on theirfabrication recipe.

As described above, ICs are typically tested for various characteristicsbefore being shipped to customers. For example, as shown in FIG. 4, ICsmay be graded in test for speed and placed in various bins (e.g., 5nanoseconds (ns), 6 ns, and 7 ns bins) according to their grading. If acustomer subsequently requests a more stringent speed grade (e.g., 4ns), ICs in one of the bins (e.g., a 5 ns bin) are retested and therebysorted into ICs that meet the more stringent speed grade (e.g., 4 nsbin) and those that do not (e.g., 5 ns bin). While this conventionalprocess sorts the ICs into separate speed grades, it makes inefficientuse of expensive and often limited testing resources by diverting thoseresources away from testing untested ICs in order to retest previouslytested ICs. Therefore, there is a need in the art for an improved methodof culling or sorting bins for ICs that meet more stringent standards,such as a higher speed grading.

As described in U.S. Pat. Nos. 5,301,143, 5,294,812, and 5,103,166, somemethods have been devised to electronically identify individual ICs.Such methods take place “off” the manufacturing line and involve the useof electrically retrievable ID codes, such as so-called “fuse IDs,”programmed into individual ICs to identify the ICs. The programming of afuse ID typically involves selectively blowing an arrangement of fusesand anti-fuses in an IC so that when the fuses or anti-fuses areaccessed, they output a selected ID code. Unfortunately, none of thesemethods address the problem of identifying and sorting ICs “on” amanufacturing line.

BRIEF SUMMARY OF THE INVENTION

An inventive method for sorting integrated circuit (IC) devices of thetype to have a substantially unique identification (ID) code, such as afuse ID, including automatically reading the ID code of each of the ICdevices and sorting the IC devices according to their automatically readID codes. The inventive method can be used in conjunction with an ICmanufacturing process that includes providing semiconductor wafers,fabricating the ICs on each of the wafers, causing each of the ICs tostore its ID code, separating each of the ICs from its wafer to form anIC die, assembling the IC dice into IC devices, and testing the ICdevices. The method can also be used in conjunction with Single In-lineMemory Module (SIMM), Dual In-line Memory Module (DIMM), and othermulti-chip module (MCM) manufacturing processes.

In another embodiment, an inventive method for recovering IC devicesfrom a group of IC devices that have previously been rejected inaccordance with a test standard that has since been relaxed includes:storing test results that caused each of the IC devices in the group tobe rejected in connection with an ID code, such as a fuse ID, associatedwith each device; automatically reading the ID code from each of the ICdevices; accessing the test results stored in connection with each ofthe automatically read ID codes; comparing the accessed test results foreach of the IC devices with the relaxed test standard; and sorting theIC devices according to whether their accessed test results pass therelaxed test standard in order to recover any of the IC devices havingtest results that pass the relaxed test standard.

By sorting the IC devices in accordance with their previously storedtest results and their ID codes, the above-described inventive methodeliminates the need to retest the IC devices after the test standard isrelaxed in order to cull shippable IC devices from the rejected devices.

In still another embodiment, a method for sorting a group of IC devicesin accordance with a first IC standard, such as a speed standard, thathave previously been sorted in accordance with a second IC standard,such as a speed standard, that is less stringent than the first ICstandard, includes storing test results that caused each of the ICdevices in the group to be sorted into the group in connection with IDcodes, such as fuse IDs, of the devices, automatically reading the IDcode from each of the IC devices, accessing the test results stored inconnection with each of the automatically read ID codes, comparing theaccessed test results for each of the IC devices with the first ICstandard, and sorting the IC devices according to whether their testresults pass the first IC standard.

In a further embodiment, an inventive back-end test method forseparating IC devices in need of enhanced reliability testing from agroup of IC devices undergoing back-end test procedures includes:storing a flag in connection with an ID code, such as a fuse ID,associated with each of the IC devices in the group indicating whethereach IC device is in need of enhanced reliability testing; automaticallyreading the ID code of each of the IC devices in the group; accessingthe enhanced reliability testing flag stored in connection with each ofthe automatically read ID codes; and sorting the IC devices inaccordance with whether their enhanced reliability testing flagindicates that they are in need of enhanced reliability testing.

Thus, the inventive method described above provides an advantageousmethod for sorting ICs from the same wafer lot into those ICs thatrequire enhanced reliability testing and those that do not.

In a still further embodiment, an inventive method in an ICmanufacturing process for testing different fabrication process recipesincludes the following: providing first and second pluralities ofsemiconductor wafers; fabricating a first plurality of ICs on each ofthe first plurality of wafers in accordance with a control recipe;fabricating a second plurality of ICs on each of the second plurality ofwafers in accordance with a test recipe; causing each of the ICs on eachof the wafers to permanently store a substantially unique ID code, suchas a fuse ID; separating each of the ICs on each of the wafers from itswafer to form one of a plurality of IC dice; assembling each of the ICdice into an IC device; automatically reading the ID code from the IC ineach of the IC devices; testing each of the IC devices; and sorting eachof the IC devices in accordance with the automatically read ID code fromthe IC in each of the IC devices indicating that the IC is from one ofthe first and second pluralities of ICs.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a flow diagram illustrating a conventional procedure in anintegrated circuit (IC) manufacturing process for culling shippable ICsfrom a reject bin;

FIG. 2 is a flow diagram illustrating a conventional procedure in an ICmanufacturing process for directing ICs to enhanced reliability testing;

FIG. 3 is a flow diagram illustrating a conventional procedure in an ICmanufacturing process for testing a new or special fabrication processrecipe;

FIG. 4 is a flow diagram illustrating a conventional procedure in an ICmanufacturing process for speed sorting ICs;

FIG. 5 is a flow diagram illustrating a procedure in an integratedcircuit (IC) manufacturing process for culling shippable ICs from areject bin in accordance with the present invention;

FIG. 6 is a flow diagram illustrating a procedure in an IC manufacturingprocess for directing ICs to enhanced reliability testing in accordancewith another embodiment of the present invention;

FIG. 7 is a flow diagram illustrating a procedure in an IC manufacturingprocess for testing a new or special fabrication process recipe inaccordance with still another embodiment of the present invention; and

FIG. 8 is a flow diagram illustrating a procedure in an IC manufacturingprocess for speed sorting ICs in accordance with a further embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

As shown in FIG. 5, an inventive method for sorting integrated circuit(IC) devices is embodied in a method 10 in an IC manufacturing processfor culling shippable ICs from a reject bin 12. It will be understood bythose having skill in the field of this invention that the presentinvention is applicable to sorting any IC devices, including DynamicRandom Access Memory (DRAM) ICs, Static Random Access Memory (SRAM) ICs,Synchronous DRAM (SDRAM) ICs, processor ICs, Single In-line MemoryModules (SIMMs), Dual In-line Memory Modules (DIMMs), and otherMulti-Chip Modules (MCMs).

The method 10 includes the step of fabricating 14 ICs on wafers from awafer lot 16. ICs fabricated on the wafers are then programmed in aprogram step 18 in the manner described above with a fuse identification(ID) unique to each IC. The fuse ID may identify a wafer lot ID, theweek the ICs were fabricated, a wafer ID, a die location on the wafer,and a fabrication facility ID. It will be understood, of course, thatthe present invention includes within its scope ICs having any ID code,including those having fuse IDs. It will also be understood that the IDcode for each IC need not be unique, but instead may only specify thewafer the IC comes from, for example.

Once programmed, the ICs proceed through an assembly step 20 to a teststep 22 where the fuse IDs are automatically read and stored inassociation with test data 24 generated in the test step 22. Althoughthe fuse IDs are typically read electronically, it will be understoodthat they may also be read optically if the fuse ID consists of “blown”laser fuses that are optically accessible. It will also be understoodthat the test data 24 may include data such as the following: dataidentifying the testing equipment that tested the ICs, operatingpersonnel who operated the testing equipment, and the set-up of theequipment when the ICs were tested; and data indicating the time anddate the ICs were tested, the yield of shippable ICs through the teststep 22, and test results for the ICs from the various stages of thetest step 22.

ICs that pass the test step 22 are typically shipped to customers, whilethose that fail the test step 22 are directed to the reject bin 12. At apoint in time when test standards of the test step 22 have been relaxedas described above, the ICs in the reject bin 12 are sorted in a sortstep 26 by reading the fuse ID of each IC, accessing the test data 24associated with the fuse ID, and comparing the accessed test data 24with the relaxed test standards. Those ICs that fail even the relaxedtest standards are directed back to the reject bin 12, while those ICsthat pass the relaxed test standards are typically shipped to customers.The method 10 thus successfully culls shippable ICs from the reject bin12 without retesting the ICs.

As shown in FIG. 6, the inventive sorting method is also embodied in aback-end (i.e., after fabrication) test method 30 for separating ICs inneed of enhanced reliability testing from a group of ICs undergoingback-end test procedures. ICs typically require enhanced reliabilitytesting because the wafer they come from is unreliable as a result offabrication errors and other unintended manufacturing processdeviations.

The method 30 includes the step 32 of fabricating ICs on wafers from awafer lot 34. ICs fabricated on the wafers are then programmed in aprogram step 36 in the manner described above with a fuse identification(ID) unique to each IC. The fuse ID may identify a wafer lot ID, theweek the ICs were fabricated, a wafer ID, a die location on the wafer,and a fabrication facility ID. It will be understood, of course, thatthe present invention includes within its scope ICs having any ID code,including those having fuse IDs. It will also be understood that the IDcode for each IC need not be unique, but instead may only specify thewafer the IC comes from, for example.

Once programmed, the ICs proceed through an assembly step 38. At thispoint in the IC manufacturing process, it is not uncommon for a numberof wafers to have been identified as being unreliable for the reasonsstated above. The fuse IDs of the ICs that come from these unreliablewafers may then be associated with a stored flag indicating the ICs comefrom unreliable wafers. If any wafers in the wafer lot 34 have beenidentified as being unreliable, the ICs proceed to a sort step 40, wheretheir fuse IDs are automatically read so the ICs can be sorted intothose flagged as coming from the unreliable wafers that requireprocessing through an enhanced reliability testing step 42 and those notflagged as coming from the unreliable wafers that may proceed through astandard test step 44. Of course, those ICs that pass either thestandard test step 44 or the enhanced reliability testing step 42 aretypically shipped to customers, while those that fail these steps aredirected to a reject bin (not shown).

Thus, the present invention provides a method 30 that directs those ICsneeding enhanced reliability testing to the enhanced reliability testingstep 42, while allowing those that do not require enhanced reliabilitytesting to proceed through the standard testing step 44.

As shown in FIG. 7, the inventive sorting method is further embodied ina method 50 for testing different fabrication process recipes. Suchtesting is typically done in accordance with a Special Work Request(SWR) from an engineer or technician.

The method 50 includes fabricating some of the wafers from a wafer lot52 in a fabrication step 54 in accordance with a control process recipethat is typically the normal process recipe in use in the ICmanufacturing process at the time. The remainder of the wafers from thewafer lot 52 is fabricated in another fabrication step 56 in accordancewith a special or test process recipe. The special or test processrecipe may change a variety of variables in the fabrication process,including doping, the thickness of IC layers, etc.

Once the ICs are fabricated in the fabrication steps 54 and 56, the ICsare then programmed in a program step 58 in the manner described abovewith a fuse identification (ID) unique to each IC. The fuse ID mayidentify a wafer lot ID, the week the ICs were fabricated, a wafer ID, adie location on the wafer, and a fabrication facility ID. It will beunderstood, of course, that the present invention includes within itsscope ICs having any ID code, including those having fuse IDs. It willalso be understood that the ID code for each IC need not be unique, butinstead may only specify the wafer the IC comes from, for example.

Once programmed, the ICs proceed through an assembly step 60 to a teststep 62 where the fuse IDs are automatically read and stored inassociation with test data 64 generated for both the control recipe ICsand the special or test recipe ICs in the test step 62. Although thefuse IDs are typically read electronically, it will be understood thatthey may also be read optically if the fuse ID consists of “blown” laserfuses that are optically accessible. It will also be understood that thetest data 64 may include data such as the following: data identifyingthe testing equipment that tested the ICs, operating personnel whooperated the testing equipment, and the set-up of the equipment when theICs were tested; and data indicating the time and date the ICs weretested, the yield of shippable ICs through the test step 62, and testresults for the ICs from the various stages of the test step 62.

Once the test data 64 is generated, the data 64 may be analyzed 67 todetermine those ICs that are shippable and those that are not, and todetermine any differences in test results between the control recipe ICsand the special or test recipe ICs. The ICs are sorted in a sort step 66so they may be shipped, reworked, repaired, retested, or rejected inaccordance with the analysis of the test results.

By sorting the control recipe 68 and special or test recipe 69 ICs atthe end of the IC manufacturing process, the method 50 is able toassemble and test the ICs together and thus eliminate unintendedvariables introduced into the process of testing the special or testrecipe by the conventional method of assembling and testing the ICsseparately. The inventive method 50 thus provides more reliable testresults.

As shown in FIG. 8, the inventive method for sorting IC devices is alsoembodied in a method 70 in an IC manufacturing process for sorting ICdevices in accordance with an IC standard, such as speed, that is morestringent than an IC standard that the devices were previously sorted inaccordance with. It will be understood that although the method of FIG.8 will be described with respect to speed sorting, the method isapplicable to all situations in which ICs previously sorted inaccordance with an IC standard, such as speed, need to be sorted inaccordance with another, more stringent IC standard. Such IC standardsmay include, for example, access time, data setup time, data hold time,standby current, refresh current, and operating current.

The method 70 includes the step 72 of fabricating ICs on wafers from awafer lot 74. ICs fabricated on the wafers are then programmed in aprogram step 76 in the manner described above with a fuse identification(ID) unique to each IC. The fuse ID may identify a wafer lot ID, theweek the ICs were fabricated, a wafer ID, a die location on the wafer,and a fabrication facility ID. It will be understood, of course, thatthe present invention includes within its scope ICs having any ID code,including those having fuse IDs.

Once programmed, the ICs proceed through an assembly step 78 to a teststep 80 where the fuse IDs are automatically read and stored inassociation with test data 82 generated in the test step 80. Althoughthe fuse IDs are typically read electronically, it will be understoodthat they may also be read optically if the fuse ID consists of “blown”laser fuses that are optically accessible. It will also be understoodthat the test data 82 includes speed-grading data for each IC, asdescribed above, and may include data such as the following: dataidentifying the testing equipment that tested the ICs, operatingpersonnel who operated the testing equipment, and the set-up of theequipment when the ICs were tested; and data indicating the time anddate the ICs were tested, the yield of shippable ICs through the teststep 80, and test results for the ICs from the various stages of thetest step 80.

ICs that pass the test step 80 are typically directed to speed-gradedbins 84, 86, and 88, while those that fail the test step 80 are directedto a reject bin 90. The speed-graded bins 84, 86, and 88 typically eachcontain ICs of varying speeds. For example, the bin 88 may contain avariety of 5.0 ns, 4.5 ns, 4.0 ns, 3.5 ns, etc., parts, the bin 86 maycontain a variety of 6.0 ns, 5.5 ns, 5.1 ns, etc., parts, and the bin 84may contain a variety of 7.0 ns, 6.5 ns, 6.1 ns, etc., parts.

On occasion, customers request ICs that meet a more stringent speedstandard (e.g., 4 nanoseconds (ns)) than any of the ICs in the variousbins 84, 86, and 88 have been graded for. While bin 88, for example, maycontain ICs that will meet the more stringent speed standard, the bin 88cannot be used to supply the customer's request because the ICs in thebin 88 have only been graded (i.e., are guaranteed to meet or exceed) alower speed standard (e.g., 5 ns). Therefore, the present inventivemethod 70 sorts the ICs in a sort step 92 by reading the fuse ID of eachIC, accessing the test data 82, including the speed-grading data,associated with the fuse ID, and comparing the accessed speed-gradingdata with the more stringent speed standard (e.g., 4 ns). Those ICs thatfail the more stringent speed standard are directed to a speed-gradedbin 94, while those ICs that pass the more stringent speed standard aredirected to another speed-graded bin 96 where they can be used to fillthe customer's request. The inventive method 70 thus sorts the ICs inaccordance with a more stringent IC standard, such as speed, than theywere previously sorted in accordance with the present invention withouthaving to retest the ICs, and thus without reusing valuable testingresources to retest ICs.

Although the present invention has been described with reference toparticular embodiments, the invention is not limited to these describedembodiments. For example, while the various steps of the embodiments ofthe inventive sorting method have been described as occurring in aparticular order, it will be understood that these steps need notnecessarily occur in the described order to fall within the scope of thepresent invention. Thus, the invention is limited only by the appendedclaims, which include within their scope, all equivalent methods thatoperate according to the principles of the invention as described.

1. A method for sorting integrated circuit (IC) devices, the methodcomprising: fabricating a plurality of integrated circuits (ICs) on eachof a plurality of wafers; causing each of the ICs on each of the wafersto store a substantially unique identification (ID) code; separatingeach of the ICs on each of the wafers from its wafer to form one of aplurality of IC dice; assembling the IC dice into IC devices; readingthe substantially unique ID codes from the ICs of the IC devices;testing each of the IC devices; and sorting each of the IC devices inaccordance with its read substantially unique ID code.
 2. The method ofclaim 1, wherein fabricating a plurality of ICs comprises fabricatingICs of one or more types including Dynamic Random Access Memory (DRAM)ICs, Static Random Access Memory (SRAM) ICs, Synchronous DRAM (SDRAM)ICs, and processor ICs.
 3. The method of claim 1, wherein causing eachof the ICs on each of the wafers to store a substantially unique ID codecomprises permanently storing a substantially unique ID code.
 4. Themethod of claim 1, wherein testing each of the IC devices comprises atleast one of hot pre-grade, burn-in, hot final, cold final, andscanning.
 5. The method of claim 1, wherein reading the substantiallyunique ID code from the ICs of the IC devices occurs before testing eachof the IC devices.
 6. The method of claim 1, wherein reading thesubstantially unique ID codes from the ICs of the IC devices comprisesautomatically reading the substantially unique ID codes.
 7. The methodof claim 1, wherein sorting each of the IC devices in accordance withtheir read substantially unique ID code comprises sorting one or more ofDynamic Random Access Memory (DRAM) IC devices, Static Random AccessMemory (SRAM) IC devices, Synchronous DRAM (SDRAM) IC devices, processorIC devices, Single In-line Memory Modules (SIMMs), Dual In-line MemoryModules (DIMMs), and other Multi-Chip Modules (MCMs).
 8. The method ofclaim 1, further comprising associating data from the testing of each ICdevice with the substantially unique ID code of that IC device.
 9. Themethod of claim 8, further comprising using the test data associatedwith the substantially unique ID code of each IC device in sorting eachof the IC devices.
 10. A method for sorting integrated circuit devices,the method comprising: fabricating a plurality of integrated circuits oneach wafer of a plurality of wafers; causing integrated circuits on eachwafer of the plurality of wafers to store a substantially uniqueidentification code thereon; separating integrated circuits on eachwafer of the plurality of wafers from their respective wafers to form aplurality of integrated circuit dice; assembling the plurality ofintegrated circuit dice into integrated circuit devices; reading thesubstantially unique identification codes from the integrated circuitsof the integrated circuit devices; testing each of the integratedcircuit devices; and sorting the integrated circuit devices inaccordance with their read, respective substantially uniqueidentification codes.
 11. The method of claim 10, wherein fabricating aplurality of integrated circuits comprises fabricating integratedcircuits of different types including one or more of Dynamic RandomAccess Memory (DRAM) ICs, Static Random Access Memory (SRAM) ICs,Synchronous DRAM (SDRAM) ICs, and processor ICs.
 12. The method of claim10, wherein causing integrated circuits on each wafer of the pluralityof wafers to store a substantially unique identification code comprisescausing the integrated circuits to permanently storing a substantiallyunique identification code.
 13. The method of claim 10, wherein testingeach of the integrated circuit devices comprises one or more of hotpre-grade, burn-in, hot final, cold final, and scanning.
 14. The methodof claim 10, wherein reading the substantially unique identificationcode from the integrated circuits of the integrated circuit devices iseffected before testing each of the integrated circuit devices.
 15. Themethod of claim 10, wherein reading the substantially uniqueidentification codes from the integrated circuits of the integratedcircuit devices comprises automatically reading the substantially uniqueidentification codes.
 16. The method of claim 10, wherein sorting theintegrated circuit devices in accordance with their read, respectivesubstantially unique identification codes comprises sorting one or moreof Dynamic Random Access Memory (DRAM) IC devices, Static Random AccessMemory (SRAM) IC devices, Synchronous DRAM (SDRAM) IC devices, processorIC devices, Single In-line Memory Modules (SIMMs), Dual In-line MemoryModules (DIMMs), and other Multi-Chip Modules (MCMs).
 17. The method ofclaim 10, further comprising associating data from the testing of eachof the integrated circuit devices with the substantially uniqueidentification code of that integrated circuit device.
 18. The method ofclaim 17, further comprising using the test data associated with thesubstantially unique identification code of each integrated circuitdevice in sorting the integrated circuit device.
 19. A method forsorting integrated circuit devices, the method comprising: fabricating aplurality of integrated circuits on each wafer of a plurality ofsemiconductor wafers; causing each of the integrated circuits on eachsemiconductor wafer of the plurality of semiconductor wafers to store asubstantially unique identification code using one of fuses, oranti-fuses, or both fuses and anti-fuses contained in each integratedcircuit device; separating each of the integrated circuits on eachsemiconductor wafer of the plurality of semiconductor wafers from itswafer to form a plurality of integrated circuit dice; assembling theplurality of integrated circuit dice into integrated circuit devices;testing each of the integrated circuit devices; automatically readingthe substantially unique identification codes from the integratedcircuits of the integrated circuit devices; and sorting each of theintegrated circuit devices in accordance with their automatically readsubstantially unique identification code.
 20. The method of claim 19,wherein fabricating a plurality of integrated circuits comprisesfabricating integrated circuits of different types including DynamicRandom Access Memory (DRAM) integrated circuits, Static Random AccessMemory (SRAM) integrated circuits, Synchronous DRAM (SDRAM) integratedcircuits, and processor integrated circuits.
 21. The method of claim 19,wherein testing each of the integrated circuit devices comprises hotpre-grade, burn-in, hot final, cold final, and scanning.
 22. The methodof claim 19, wherein automatically reading the substantially uniqueidentification codes from the integrated circuits of the integratedcircuit devices is performed before testing each of the integratedcircuit devices.
 23. The method of claim 19, further comprisingassociating data from the testing of each of the integrated circuitdevices with the substantially unique identification code of thatintegrated circuit device.
 24. The method of claim 23, furthercomprising using the test data associated with the substantially uniqueidentification code of each integrated circuit device in sorting each ofthe integrated circuit devices.